GL3310 usb 3.0 to sata 3gb/s bridge controller product overview genesys logic, inc.
GL3310 product overview ?2012 genesys logic, inc. - all rights reserved. page 2 copyright copyright ? 2012 genesys logic, inc. all rights reserved. no part of the materials shall be reproduced in any form or by any means without prior written consent of genesys logic, inc. ownership and title genesys logic, inc. owns and retains of its right, title and interest in and to all materials provided herein. genesys logic, inc. reserves all rights, including, but not limited to, all patent rights, trademarks, copyrights and any other propriety rights. no license is granted hereunder. disclaimer all materials are provided ?as is?. genesys logic, inc. makes no warranties, express, implied or otherwise, regarding their accuracy, merchantability, fitness for an y particular purpose, an d non-infringement of intellectual property. in no event shall genesys logic, inc. be liable for any damages, including, without limitation, any direct, indirect, consequential, or incidental damages. the materials may contain errors or omissions. genesys logic, inc. may make changes to the materials or to the products described herein at anytime without notice. genesys logic, inc. 12f., no. 205, sec. 3, beixin rd., xindian dist. 231, new taipei city, taiwan tel : (886-2) 8913-1888 fax : (886-2) 6629-6168 http://www.genesyslogic.com
GL3310 product overview ?2012 genesys logic, inc. - all rights reserved. page 3 general description the GL3310 is a highly integrated usb 3.0 to sata 3gb/s bridge controller, which includes self-developed usb 3.0 superspeed transmitter/receiver physical laye r (phy), usb 2.0 highspeed phy, and serial ata (sata) phy. it also backwards supports usb 2.0 and sata 1.5gb/s. this single chip solution complies with universal serial bus specification revision 2.0, universal serial bus 3.0 specification revision 1.0, and serial ata revision 3.0 specification gold revision. genesys logic, inc. has been developing, manufacturing, and distributing usb applications and products for more than ten years. with the experienced skills, the se lf-developed usb 3.0 superspeed transceiver exhibits surprising achievement as shown in figure 1.1. the signal quality not only fits in the specification limitation, but also provides wide tolerance for unexpected conditions. as a result, GL3310 can perform fast transmission rate and high compatibility with various usb hosts and commercial sata devices. genesys superspeed tx eye diagram and rx jitter tolerance GL3310 is especially designed for cost-efficient solution. the 8051 microcontroller, embedded power regulators, and single 25 mhz clock source all are the features help customers easily design their own products with few efforts. this highly integrated solution helps to reduce system cost as well. moreover, GL3310 inherits customer feedbacks from its predecessor products and provides two spi interfaces, pwm controls, watchdog timers, ua rt monitoring interface, and variou s general purpose i/os (gpio). these flexible add-on features help the customer to design specific products for applications.
GL3310 product overview ?2012 genesys logic, inc. - all rights reserved. page 4 features usb specification compliance ? comply with universal serial bus 3.0 specification rev. 1.0 (usb 3.0) ? comply with universal serial bus specification rev. 2.0 (usb 2.0) ? comply with usb mass storage class specification rev. 1.0 ? support usb mass storage class bulk-only transport (bot) ? support 1 device address and up to 6 endpoints: control (0) / bulk data write out (1) / bulk data read in (2) / interrupt in (3) / cmd out (4) / status in (5) ? support 5 gbps superspeed, 480 mbps high-speed, and 12 mbps full-speed transfer rates sata specification features ? comply with serial ata revision 3.0 specification gold revision ? support sata power saving, including partial and slumber modes ? support sata hot plug ? support native command queuing up to 32 commands ? support sata host/device initiated power management ? support sata bist host/device initiated eye pattern test ? support 3.0 gbps and 1.5 gbps transfer rates embedded 8051 micro-controller ? embedded 16 kbytes mask rom and internal 48 kbytes sram embedded 5v-to-3.3v and 3.3v-to-1.2v regulators ? no external regulators required ? 5 v / 3.3 v power sources single 25 mhz clock source available in 48-pin qfn (7 x 7 mm 2 ) and 64-pin lqfp (7 x 7 mm 2 ) packages other features ? spread spectrum clocking (ssc) for emi reduction ? on-chip watchdog timer for automatic error recovery ? primary spi interface for firmware update ? secondary spi interface for display controller ? pwm interfaces for fan control and led control (2 gpios) ? uart interface for debugging
GL3310 product overview ?2012 genesys logic, inc. - all rights reserved. page 5 block diagram
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